/*
 * @Author: Laputa
 * @Version: V0.0
 * @Date: 2023-05-31 14:49:57
 * @LastEditors: Laputa
 * @LastEditTime: 2023-12-06 16:43:11
 * @Description: This file contains the functions prototypes for the EIC firmware library.
 *
 * Copyright (c) 2023 by Levetop, All Rights Reserved.
 */

#ifndef _LT168_EIC_H
#define _LT168_EIC_H

#include "LT168.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/* ICSR */

#define EIC_ICSR_VEC_MASK                        (0x7FU)
#define EIC_ICSR_VEC_SHIFT                       (0U)

#define EIC_ICSR_CLRPTRAP_MASK                   (0x8000000U)
#define EIC_ICSR_CLRPTRAP_SHIFT                  (27U)
#define EIC_ICSR_CLRPTRAP(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_ICSR_CLRPTRAP_SHIFT)) & EIC_ICSR_CLRPTRAP_MASK)

#define EIC_ICSR_SETPTRAP_MASK                   (0x10000000U)
#define EIC_ICSR_SETPTRAP_SHIFT                  (28U)
#define EIC_ICSR_SETPTRAP(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_ICSR_SETPTRAP_SHIFT)) & EIC_ICSR_SETPTRAP_MASK)

#define EIC_ICSR_SRST_MASK                       (0x80000000U)
#define EIC_ICSR_SRST_SHIFT                      (31U)
#define EIC_ICSR_SRST(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_ICSR_SRST_SHIFT)) & EIC_ICSR_SRST_MASK)

/* IER */
#define EIC_IER_ADC_MASK                         (0x1U)
#define EIC_IER_ADC_SHIFT                        (0U)
#define EIC_IER_ADC(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_ADC_SHIFT)) & EIC_IER_ADC_MASK)

#define EIC_IER_QSPI0_MASK                       (0x2U)
#define EIC_IER_QSPI0_SHIFT                      (1U)
#define EIC_IER_QSPI0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IER_QSPI0_SHIFT)) & EIC_IER_QSPI0_MASK)

#define EIC_IER_SCI0_MASK                        (0x4U)
#define EIC_IER_SCI0_SHIFT                       (2U)
#define EIC_IER_SCI0(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_SCI0_SHIFT)) & EIC_IER_SCI0_MASK)

#define EIC_IER_COMP0_MASK                       (0x8U)
#define EIC_IER_COMP0_SHIFT                      (3U)
#define EIC_IER_COMP0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IER_COMP0_SHIFT)) & EIC_IER_COMP0_MASK)

#define EIC_IER_COMP1_MASK                       (0x10U)
#define EIC_IER_COMP1_SHIFT                      (4U)
#define EIC_IER_COMP1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IER_COMP1_SHIFT)) & EIC_IER_COMP1_MASK)

#define EIC_IER_DMA_MASK                         (0x20U)
#define EIC_IER_DMA_SHIFT                        (5U)
#define EIC_IER_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_DMA_SHIFT)) & EIC_IER_DMA_MASK)

#define EIC_IER_WDT_MASK                         (0x40U)
#define EIC_IER_WDT_SHIFT                        (6U)
#define EIC_IER_WDT(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_WDT_SHIFT)) & EIC_IER_WDT_MASK)

#define EIC_IER_PWM0_MASK                        (0x80U)
#define EIC_IER_PWM0_SHIFT                       (7U)
#define EIC_IER_PWM0(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PWM0_SHIFT)) & EIC_IER_PWM0_MASK)

#define EIC_IER_PWM1_MASK                        (0x100U)
#define EIC_IER_PWM1_SHIFT                       (8U)
#define EIC_IER_PWM1(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PWM1_SHIFT)) & EIC_IER_PWM1_MASK)

#define EIC_IER_PIT0_MASK                        (0x200U)
#define EIC_IER_PIT0_SHIFT                       (9U)
#define EIC_IER_PIT0(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PIT0_SHIFT)) & EIC_IER_PIT0_MASK)

#define EIC_IER_PIT1_MASK                        (0x400U)
#define EIC_IER_PIT1_SHIFT                       (10U)
#define EIC_IER_PIT1(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PIT1_SHIFT)) & EIC_IER_PIT1_MASK)

#define EIC_IER_PIT2_MASK                        (0x800U)
#define EIC_IER_PIT2_SHIFT                       (11U)
#define EIC_IER_PIT2(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PIT2_SHIFT)) & EIC_IER_PIT2_MASK)

#define EIC_IER_PIT3_MASK                        (0x1000U)
#define EIC_IER_PIT3_SHIFT                       (12U)
#define EIC_IER_PIT3(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_PIT3_SHIFT)) & EIC_IER_PIT3_MASK)

#define EIC_IER_RTC_MASK                         (0x2000U)
#define EIC_IER_RTC_SHIFT                        (13U)
#define EIC_IER_RTC(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_RTC_SHIFT)) & EIC_IER_RTC_MASK)

#define EIC_IER_USB_MASK                         (0x4000U)
#define EIC_IER_USB_SHIFT                        (14U)
#define EIC_IER_USB(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_USB_SHIFT)) & EIC_IER_USB_MASK)

#define EIC_IER_I2C_MASK                         (0x8000U)
#define EIC_IER_I2C_SHIFT                        (15U)
#define EIC_IER_I2C(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_I2C_SHIFT)) & EIC_IER_I2C_MASK)

#define EIC_IER_EPORT2_MASK                      (0x10000U)
#define EIC_IER_EPORT2_SHIFT                     (16U)
#define EIC_IER_EPORT2(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IER_EPORT2_SHIFT)) & EIC_IER_EPORT2_MASK)

#define EIC_IER_PVD_MASK                         (0x20000U)
#define EIC_IER_PVD_SHIFT                        (17U)
#define EIC_IER_PVD(x)                           (((uint32_t)(((uint32_t)(x)) << EIC_IER_PVD_SHIFT)) & EIC_IER_PVD_MASK)

#define EIC_IER_CAN_IFRH_MASK                    (0x40000U)
#define EIC_IER_CAN_IFRH_SHIFT                   (18U)
#define EIC_IER_CAN_IFRH(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_IFRH_SHIFT)) & EIC_IER_CAN_IFRH_MASK)

#define EIC_IER_CAN_BOFF_MASK                    (0x80000U)
#define EIC_IER_CAN_BOFF_SHIFT                   (19U)
#define EIC_IER_CAN_BOFF(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_BOFF_SHIFT)) & EIC_IER_CAN_BOFF_MASK)

#define EIC_IER_CAN_ERR_MASK                     (0x100000U)
#define EIC_IER_CAN_ERR_SHIFT                    (20U)
#define EIC_IER_CAN_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_ERR_SHIFT)) & EIC_IER_CAN_ERR_MASK)

#define EIC_IER_CAN_TWRN_MASK                    (0x200000U)
#define EIC_IER_CAN_TWRN_SHIFT                   (21U)
#define EIC_IER_CAN_TWRN(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_TWRN_SHIFT)) & EIC_IER_CAN_TWRN_MASK)

#define EIC_IER_CAN_RWRN_MASK                    (0x400000U)
#define EIC_IER_CAN_RWRN_SHIFT                   (22U)
#define EIC_IER_CAN_RWRN(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_RWRN_SHIFT)) & EIC_IER_CAN_RWRN_MASK)

#define EIC_IER_CAN_WKUP_MASK                    (0x800000U)
#define EIC_IER_CAN_WKUP_SHIFT                   (23U)
#define EIC_IER_CAN_WKUP(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IER_CAN_WKUP_SHIFT)) & EIC_IER_CAN_WKUP_MASK)

#define EIC_IER_BLENDER_MASK                     (0x1000000U)
#define EIC_IER_BLENDER_SHIFT                    (24U)
#define EIC_IER_BLENDER(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IER_BLENDER_SHIFT)) & EIC_IER_BLENDER_MASK)

#define EIC_IER_RGBC_MASK                        (0x2000000U)
#define EIC_IER_RGBC_SHIFT                       (25U)
#define EIC_IER_RGBC(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_RGBC_SHIFT)) & EIC_IER_RGBC_MASK)

#define EIC_IER_QSPI1_MASK                       (0x4000000U)
#define EIC_IER_QSPI1_SHIFT                      (26U)
#define EIC_IER_QSPI1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IER_QSPI1_SHIFT)) & EIC_IER_QSPI1_MASK)

#define EIC_IER_QSPI2_MASK                       (0x8000000U)
#define EIC_IER_QSPI2_SHIFT                      (27U)
#define EIC_IER_QSPI2(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IER_QSPI2_SHIFT)) & EIC_IER_QSPI2_MASK)

#define EIC_IER_SCI1_MASK                        (0x10000000U)
#define EIC_IER_SCI1_SHIFT                       (28U)
#define EIC_IER_SCI1(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_SCI1_SHIFT)) & EIC_IER_SCI1_MASK)

#define EIC_IER_SCI2_MASK                        (0x20000000U)
#define EIC_IER_SCI2_SHIFT                       (29U)
#define EIC_IER_SCI2(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IER_SCI2_SHIFT)) & EIC_IER_SCI2_MASK)

#define EIC_IER_EPORT0_MASK                      (0x40000000U)
#define EIC_IER_EPORT0_SHIFT                     (30U)
#define EIC_IER_EPORT0(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IER_EPORT0_SHIFT)) & EIC_IER_EPORT0_MASK)

#define EIC_IER_EPORT1_MASK                      (0x80000000U)
#define EIC_IER_EPORT1_SHIFT                     (31U)
#define EIC_IER_EPORT1(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IER_EPORT1_SHIFT)) & EIC_IER_EPORT1_MASK)

/* IPSR */
#define EIC_IPSR_ADC_MASK                        (0x1U)
#define EIC_IPSR_ADC_SHIFT                       (0U)
#define EIC_IPSR_ADC(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_ADC_SHIFT)) & EIC_IPSR_ADC_MASK)

#define EIC_IPSR_QSPI0_MASK                      (0x2U)
#define EIC_IPSR_QSPI0_SHIFT                     (1U)
#define EIC_IPSR_QSPI0(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_QSPI0_SHIFT)) & EIC_IPSR_QSPI0_MASK)

#define EIC_IPSR_SCI0_MASK                       (0x4U)
#define EIC_IPSR_SCI0_SHIFT                      (2U)
#define EIC_IPSR_SCI0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_SCI0_SHIFT)) & EIC_IPSR_SCI0_MASK)

#define EIC_IPSR_COMP0_MASK                      (0x8U)
#define EIC_IPSR_COMP0_SHIFT                     (3U)
#define EIC_IPSR_COMP0(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_COMP0_SHIFT)) & EIC_IPSR_COMP0_MASK)

#define EIC_IPSR_COMP1_MASK                      (0x10U)
#define EIC_IPSR_COMP1_SHIFT                     (4U)
#define EIC_IPSR_COMP1(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_COMP1_SHIFT)) & EIC_IPSR_COMP1_MASK)

#define EIC_IPSR_DMA_MASK                        (0x20U)
#define EIC_IPSR_DMA_SHIFT                       (5U)
#define EIC_IPSR_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_DMA_SHIFT)) & EIC_IPSR_DMA_MASK)

#define EIC_IPSR_WDT_MASK                        (0x40U)
#define EIC_IPSR_WDT_SHIFT                       (6U)
#define EIC_IPSR_WDT(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_WDT_SHIFT)) & EIC_IPSR_WDT_MASK)

#define EIC_IPSR_PWM0_MASK                       (0x80U)
#define EIC_IPSR_PWM0_SHIFT                      (7U)
#define EIC_IPSR_PWM0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PWM0_SHIFT)) & EIC_IPSR_PWM0_MASK)

#define EIC_IPSR_PWM1_MASK                       (0x100U)
#define EIC_IPSR_PWM1_SHIFT                      (8U)
#define EIC_IPSR_PWM1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PWM1_SHIFT)) & EIC_IPSR_PWM1_MASK)

#define EIC_IPSR_PIT0_MASK                       (0x200U)
#define EIC_IPSR_PIT0_SHIFT                      (9U)
#define EIC_IPSR_PIT0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PIT0_SHIFT)) & EIC_IPSR_PIT0_MASK)

#define EIC_IPSR_PIT1_MASK                       (0x400U)
#define EIC_IPSR_PIT1_SHIFT                      (10U)
#define EIC_IPSR_PIT1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PIT1_SHIFT)) & EIC_IPSR_PIT1_MASK)

#define EIC_IPSR_PIT2_MASK                       (0x800U)
#define EIC_IPSR_PIT2_SHIFT                      (11U)
#define EIC_IPSR_PIT2(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PIT2_SHIFT)) & EIC_IPSR_PIT2_MASK)

#define EIC_IPSR_PIT3_MASK                       (0x1000U)
#define EIC_IPSR_PIT3_SHIFT                      (12U)
#define EIC_IPSR_PIT3(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PIT3_SHIFT)) & EIC_IPSR_PIT3_MASK)

#define EIC_IPSR_RTC_MASK                        (0x2000U)
#define EIC_IPSR_RTC_SHIFT                       (13U)
#define EIC_IPSR_RTC(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_RTC_SHIFT)) & EIC_IPSR_RTC_MASK)

#define EIC_IPSR_USB_MASK                        (0x4000U)
#define EIC_IPSR_USB_SHIFT                       (14U)
#define EIC_IPSR_USB(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_USB_SHIFT)) & EIC_IPSR_USB_MASK)

#define EIC_IPSR_I2C_MASK                        (0x8000U)
#define EIC_IPSR_I2C_SHIFT                       (15U)
#define EIC_IPSR_I2C(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_I2C_SHIFT)) & EIC_IPSR_I2C_MASK)

#define EIC_IPSR_EPORT2_MASK                     (0x10000U)
#define EIC_IPSR_EPORT2_SHIFT                    (16U)
#define EIC_IPSR_EPORT2(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_EPORT2_SHIFT)) & EIC_IPSR_EPORT2_MASK)

#define EIC_IPSR_PVD_MASK                        (0x20000U)
#define EIC_IPSR_PVD_SHIFT                       (17U)
#define EIC_IPSR_PVD(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_PVD_SHIFT)) & EIC_IPSR_PVD_MASK)

#define EIC_IPSR_CAN_IFRH_MASK                   (0x40000U)
#define EIC_IPSR_CAN_IFRH_SHIFT                  (18U)
#define EIC_IPSR_CAN_IFRH(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_IFRH_SHIFT)) & EIC_IPSR_CAN_IFRH_MASK)

#define EIC_IPSR_CAN_BOFF_MASK                   (0x80000U)
#define EIC_IPSR_CAN_BOFF_SHIFT                  (19U)
#define EIC_IPSR_CAN_BOFF(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_BOFF_SHIFT)) & EIC_IPSR_CAN_BOFF_MASK)

#define EIC_IPSR_CAN_ERR_MASK                    (0x100000U)
#define EIC_IPSR_CAN_ERR_SHIFT                   (20U)
#define EIC_IPSR_CAN_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_ERR_SHIFT)) & EIC_IPSR_CAN_ERR_MASK)

#define EIC_IPSR_CAN_TWRN_MASK                   (0x200000U)
#define EIC_IPSR_CAN_TWRN_SHIFT                  (21U)
#define EIC_IPSR_CAN_TWRN(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_TWRN_SHIFT)) & EIC_IPSR_CAN_TWRN_MASK)

#define EIC_IPSR_CAN_RWRN_MASK                   (0x400000U)
#define EIC_IPSR_CAN_RWRN_SHIFT                  (22U)
#define EIC_IPSR_CAN_RWRN(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_RWRN_SHIFT)) & EIC_IPSR_CAN_RWRN_MASK)

#define EIC_IPSR_CAN_WKUP_MASK                   (0x800000U)
#define EIC_IPSR_CAN_WKUP_SHIFT                  (23U)
#define EIC_IPSR_CAN_WKUP(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_CAN_WKUP_SHIFT)) & EIC_IPSR_CAN_WKUP_MASK)

#define EIC_IPSR_BLENDER_MASK                    (0x1000000U)
#define EIC_IPSR_BLENDER_SHIFT                   (24U)
#define EIC_IPSR_BLENDER(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_BLENDER_SHIFT)) & EIC_IPSR_BLENDER_MASK)

#define EIC_IPSR_RGBC_MASK                       (0x2000000U)
#define EIC_IPSR_RGBC_SHIFT                      (25U)
#define EIC_IPSR_RGBC(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_RGBC_SHIFT)) & EIC_IPSR_RGBC_MASK)

#define EIC_IPSR_QSPI1_MASK                      (0x4000000U)
#define EIC_IPSR_QSPI1_SHIFT                     (26U)
#define EIC_IPSR_QSPI1(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_QSPI1_SHIFT)) & EIC_IPSR_QSPI1_MASK)

#define EIC_IPSR_QSPI2_MASK                      (0x8000000U)
#define EIC_IPSR_QSPI2_SHIFT                     (27U)
#define EIC_IPSR_QSPI2(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_QSPI2_SHIFT)) & EIC_IPSR_QSPI2_MASK)

#define EIC_IPSR_SCI1_MASK                       (0x10000000U)
#define EIC_IPSR_SCI1_SHIFT                      (28U)
#define EIC_IPSR_SCI1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_SCI1_SHIFT)) & EIC_IPSR_SCI1_MASK)

#define EIC_IPSR_SCI2_MASK                       (0x20000000U)
#define EIC_IPSR_SCI2_SHIFT                      (29U)
#define EIC_IPSR_SCI2(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_SCI2_SHIFT)) & EIC_IPSR_SCI2_MASK)

#define EIC_IPSR_EPORT0_MASK                     (0x40000000U)
#define EIC_IPSR_EPORT0_SHIFT                    (30U)
#define EIC_IPSR_EPORT0(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_EPORT0_SHIFT)) & EIC_IPSR_EPORT0_MASK)

#define EIC_IPSR_EPORT1_MASK                     (0x80000000U)
#define EIC_IPSR_EPORT1_SHIFT                    (31U)
#define EIC_IPSR_EPORT1(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPSR_EPORT1_SHIFT)) & EIC_IPSR_EPORT1_MASK)

/* IPCR */
#define EIC_IPCR_ADC_MASK                        (0x1U)
#define EIC_IPCR_ADC_SHIFT                       (0U)
#define EIC_IPCR_ADC(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_ADC_SHIFT)) & EIC_IPCR_ADC_MASK)

#define EIC_IPCR_QSPI0_MASK                      (0x2U)
#define EIC_IPCR_QSPI0_SHIFT                     (1U)
#define EIC_IPCR_QSPI0(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_QSPI0_SHIFT)) & EIC_IPCR_QSPI0_MASK)

#define EIC_IPCR_SCI0_MASK                       (0x4U)
#define EIC_IPCR_SCI0_SHIFT                      (2U)
#define EIC_IPCR_SCI0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_SCI0_SHIFT)) & EIC_IPCR_SCI0_MASK)

#define EIC_IPCR_COMP0_MASK                      (0x8U)
#define EIC_IPCR_COMP0_SHIFT                     (3U)
#define EIC_IPCR_COMP0(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_COMP0_SHIFT)) & EIC_IPCR_COMP0_MASK)

#define EIC_IPCR_COMP1_MASK                      (0x10U)
#define EIC_IPCR_COMP1_SHIFT                     (4U)
#define EIC_IPCR_COMP1(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_COMP1_SHIFT)) & EIC_IPCR_COMP1_MASK)

#define EIC_IPCR_DMA_MASK                        (0x20U)
#define EIC_IPCR_DMA_SHIFT                       (5U)
#define EIC_IPCR_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_DMA_SHIFT)) & EIC_IPCR_DMA_MASK)

#define EIC_IPCR_WDT_MASK                        (0x40U)
#define EIC_IPCR_WDT_SHIFT                       (6U)
#define EIC_IPCR_WDT(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_WDT_SHIFT)) & EIC_IPCR_WDT_MASK)

#define EIC_IPCR_PWM0_MASK                       (0x80U)
#define EIC_IPCR_PWM0_SHIFT                      (7U)
#define EIC_IPCR_PWM0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PWM0_SHIFT)) & EIC_IPCR_PWM0_MASK)

#define EIC_IPCR_PWM1_MASK                       (0x100U)
#define EIC_IPCR_PWM1_SHIFT                      (8U)
#define EIC_IPCR_PWM1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PWM1_SHIFT)) & EIC_IPCR_PWM1_MASK)

#define EIC_IPCR_PIT0_MASK                       (0x200U)
#define EIC_IPCR_PIT0_SHIFT                      (9U)
#define EIC_IPCR_PIT0(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PIT0_SHIFT)) & EIC_IPCR_PIT0_MASK)

#define EIC_IPCR_PIT1_MASK                       (0x400U)
#define EIC_IPCR_PIT1_SHIFT                      (10U)
#define EIC_IPCR_PIT1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PIT1_SHIFT)) & EIC_IPCR_PIT1_MASK)

#define EIC_IPCR_PIT2_MASK                       (0x800U)
#define EIC_IPCR_PIT2_SHIFT                      (11U)
#define EIC_IPCR_PIT2(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PIT2_SHIFT)) & EIC_IPCR_PIT2_MASK)

#define EIC_IPCR_PIT3_MASK                       (0x1000U)
#define EIC_IPCR_PIT3_SHIFT                      (12U)
#define EIC_IPCR_PIT3(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PIT3_SHIFT)) & EIC_IPCR_PIT3_MASK)

#define EIC_IPCR_RTC_MASK                        (0x2000U)
#define EIC_IPCR_RTC_SHIFT                       (13U)
#define EIC_IPCR_RTC(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_RTC_SHIFT)) & EIC_IPCR_RTC_MASK)

#define EIC_IPCR_USB_MASK                        (0x4000U)
#define EIC_IPCR_USB_SHIFT                       (14U)
#define EIC_IPCR_USB(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_USB_SHIFT)) & EIC_IPCR_USB_MASK)

#define EIC_IPCR_I2C_MASK                        (0x8000U)
#define EIC_IPCR_I2C_SHIFT                       (15U)
#define EIC_IPCR_I2C(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_I2C_SHIFT)) & EIC_IPCR_I2C_MASK)

#define EIC_IPCR_EPORT2_MASK                     (0x10000U)
#define EIC_IPCR_EPORT2_SHIFT                    (16U)
#define EIC_IPCR_EPORT2(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_EPORT2_SHIFT)) & EIC_IPCR_EPORT2_MASK)

#define EIC_IPCR_PVD_MASK                        (0x20000U)
#define EIC_IPCR_PVD_SHIFT                       (17U)
#define EIC_IPCR_PVD(x)                          (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_PVD_SHIFT)) & EIC_IPCR_PVD_MASK)

#define EIC_IPCR_CAN_IFRH_MASK                   (0x40000U)
#define EIC_IPCR_CAN_IFRH_SHIFT                  (18U)
#define EIC_IPCR_CAN_IFRH(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_IFRH_SHIFT)) & EIC_IPCR_CAN_IFRH_MASK)

#define EIC_IPCR_CAN_BOFF_MASK                   (0x80000U)
#define EIC_IPCR_CAN_BOFF_SHIFT                  (19U)
#define EIC_IPCR_CAN_BOFF(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_BOFF_SHIFT)) & EIC_IPCR_CAN_BOFF_MASK)

#define EIC_IPCR_CAN_ERR_MASK                    (0x100000U)
#define EIC_IPCR_CAN_ERR_SHIFT                   (20U)
#define EIC_IPCR_CAN_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_ERR_SHIFT)) & EIC_IPCR_CAN_ERR_MASK)

#define EIC_IPCR_CAN_TWRN_MASK                   (0x200000U)
#define EIC_IPCR_CAN_TWRN_SHIFT                  (21U)
#define EIC_IPCR_CAN_TWRN(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_TWRN_SHIFT)) & EIC_IPCR_CAN_TWRN_MASK)

#define EIC_IPCR_CAN_RWRN_MASK                   (0x400000U)
#define EIC_IPCR_CAN_RWRN_SHIFT                  (22U)
#define EIC_IPCR_CAN_RWRN(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_RWRN_SHIFT)) & EIC_IPCR_CAN_RWRN_MASK)

#define EIC_IPCR_CAN_WKUP_MASK                   (0x800000U)
#define EIC_IPCR_CAN_WKUP_SHIFT                  (23U)
#define EIC_IPCR_CAN_WKUP(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_CAN_WKUP_SHIFT)) & EIC_IPCR_CAN_WKUP_MASK)

#define EIC_IPCR_BLENDER_MASK                    (0x1000000U)
#define EIC_IPCR_BLENDER_SHIFT                   (24U)
#define EIC_IPCR_BLENDER(x)                      (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_BLENDER_SHIFT)) & EIC_IPCR_BLENDER_MASK)

#define EIC_IPCR_RGBC_MASK                       (0x2000000U)
#define EIC_IPCR_RGBC_SHIFT                      (25U)
#define EIC_IPCR_RGBC(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_RGBC_SHIFT)) & EIC_IPCR_RGBC_MASK)

#define EIC_IPCR_QSPI1_MASK                      (0x4000000U)
#define EIC_IPCR_QSPI1_SHIFT                     (26U)
#define EIC_IPCR_QSPI1(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_QSPI1_SHIFT)) & EIC_IPCR_QSPI1_MASK)

#define EIC_IPCR_QSPI2_MASK                      (0x8000000U)
#define EIC_IPCR_QSPI2_SHIFT                     (27U)
#define EIC_IPCR_QSPI2(x)                        (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_QSPI2_SHIFT)) & EIC_IPCR_QSPI2_MASK)

#define EIC_IPCR_SCI1_MASK                       (0x10000000U)
#define EIC_IPCR_SCI1_SHIFT                      (28U)
#define EIC_IPCR_SCI1(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_SCI1_SHIFT)) & EIC_IPCR_SCI1_MASK)

#define EIC_IPCR_SCI2_MASK                       (0x20000000U)
#define EIC_IPCR_SCI2_SHIFT                      (29U)
#define EIC_IPCR_SCI2(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_SCI2_SHIFT)) & EIC_IPCR_SCI2_MASK)

#define EIC_IPCR_EPORT0_MASK                     (0x40000000U)
#define EIC_IPCR_EPORT0_SHIFT                    (30U)
#define EIC_IPCR_EPORT0(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_EPORT0_SHIFT)) & EIC_IPCR_EPORT0_MASK)

#define EIC_IPCR_EPORT1_MASK                     (0x80000000U)
#define EIC_IPCR_EPORT1_SHIFT                    (31U)
#define EIC_IPCR_EPORT1(x)                       (((uint32_t)(((uint32_t)(x)) << EIC_IPCR_EPORT1_SHIFT)) & EIC_IPCR_EPORT1_MASK)

/* PLSR */
#define EIC_PLSR_PLSR_MASK                       (0xC0U)
#define EIC_PLSR_PLSR_SHIFT                      (6U)
#define EIC_PLSR_PLSR(x)                         (((uint32_t)(((uint32_t)(x)) << EIC_PLSR_PLSR_SHIFT)) & EIC_PLSR_PLSR_MASK)

/* SYSPLSR */
#define EIC_SYSPLSR_SIPRI_MASK                   (0xC00000U)
#define EIC_SYSPLSR_SIPRI_SHIFT                  (22U)
#define EIC_SYSPLSR_SIPRI(x)                     (((uint32_t)(((uint32_t)(x)) << EIC_SYSPLSR_SIPRI_SHIFT)) & EIC_SYSPLSR_SIPRI_MASK)

#define EIC_SYSPLSR_EPTPRI_MASK                  (0xC0000000U)
#define EIC_SYSPLSR_EPTPRI_SHIFT                 (30U)
#define EIC_SYSPLSR_EPTPRI(x)                    (((uint32_t)(((uint32_t)(x)) << EIC_SYSPLSR_EPTPRI_SHIFT)) & EIC_SYSPLSR_EPTPRI_MASK)



/**
 * @brief: Interrupt Source Enumeration
 */
typedef enum
{
  EIC_IT_ADC            = 0,      /*!< ADC Interrupt */
  EIC_IT_QSPI0          = 1,      /*!< QSPI0 Interrupt */
  EIC_IT_SCI0           = 2,      /*!< SCI0 Interrupt */
  EIC_IT_COMP0          = 3,      /*!< COMP0 Interrupt */
  EIC_IT_COMP1          = 4,      /*!< COMP1 Interrupt */
  EIC_IT_DMAC           = 5,      /*!< DMAC Interrupt */
  EIC_IT_WDT            = 6,      /*!< WDT Interrupt */
  EIC_IT_PWM0           = 7,      /*!< PWM0 Interrupt */
  EIC_IT_PWM1           = 8,      /*!< PWM1 Interrupt */
  EIC_IT_PIT0           = 9,      /*!< PIT0 Interrupt */
  EIC_IT_PIT1           = 10,     /*!< PIT1 Interrupt */
  EIC_IT_PIT2           = 11,     /*!< PIT2 Interrupt */
  EIC_IT_PIT3           = 12,     /*!< PIT3 Interrupt */
  EIC_IT_RTC            = 13,     /*!< RTC Interrupt */
  EIC_IT_USB_DEV        = 14,     /*!< USB Interrupt */
  EIC_IT_I2C            = 15,     /*!< I2C Interrupt */
  EIC_IT_EPORT2         = 16,     /*!< EPORT2 Interrupt */
  EIC_IT_PVD            = 17,     /*!< PVD Interrupt */
  EIC_IT_CANBUS_BUFFER  = 18,     /*!< CANBUS_BUFFER Interrupt */
  EIC_IT_CANBUS_BUS_OFF = 19,     /*!< CANBUS_BUS_OFF Interrupt */
  EIC_IT_CANBUS_ERROR   = 20,     /*!< CANBUS_ERROR Interrupt */
  EIC_IT_CANBUS_TWRN    = 21,     /*!< CANBUS_TWRN Interrupt */
  EIC_IT_CANBUS_RWRN    = 22,     /*!< CANBUS_RWRN Interrupt */
  EIC_IT_CANBUS_WKUP    = 23,     /*!< CANBUS_WKUP Interrupt */
  EIC_IT_BLENDER        = 24,     /*!< BLENDER Interrupt */
  EIC_IT_RGBC           = 25,     /*!< RGB Interrupt */
  EIC_IT_QSPI1          = 26,     /*!< QSPI1 Interrupt */
  EIC_IT_QSPI2          = 27,     /*!< QSPI2 Interrupt */
  EIC_IT_SCI1           = 28,     /*!< SCI1 Interrupt */
  EIC_IT_SCI2           = 29,     /*!< SCI2 Interrupt */
  EIC_IT_EPORT0         = 30,     /*!< EPORT0 Interrupt */
  EIC_IT_EPORT1         = 31      /*!< EPORT1 Interrupt */
} eic_interrupt_source_te;

/**
 * @brief Interrupt Priority Level Enumeration
 */
typedef enum
{
  EIC_IT_Priority_0   = 0,
  EIC_IT_Priority_64  = 1,
  EIC_IT_Priority_128 = 2,
  EIC_IT_Priority_192 = 3
} eic_interrupt_priority_level_te;

/*!<---------------End of Definitions--------------->!*/

/*******************************************************************************
 * APIs
 ******************************************************************************/

/* EIC Functions*/
void EIC_System_Software_Reset(void);

void EIC_Set_Interrupt_Priority_Level(eic_interrupt_source_te int_source, eic_interrupt_priority_level_te level);
void EIC_Set_EPT_Priority_Level(eic_interrupt_priority_level_te level);

void EIC_Cmd_Interrupt(eic_interrupt_source_te int_source, FunctionState state);
void EIC_Close_ALL_Module_Interrupt(void);
/*!<---------------End of APIs--------------->!*/
#endif
/*!<---------------End of _LT168_EIC_H --------------->!*/
